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ADE7816
Data Sheet
Register
Bit
Bit Length During
Default
Address
0xE607
0xE608
Name
Period
CHNOLOAD
R/W 1
R
R
Length
16
16
Communication 2
16
16
Type 3
U
U
Value 4
N/A
N/A
Description
Line period.
Channel no load register.
0xE609 to
0xE60B
Reserved
For proper operation, do not write to
these addresses.
0xE60C
0xE60D
0xE60E
0xE60F
LINECYC
ZXTOUT
COMPMODE
Gain
R/W
R/W
R/W
R/W
16
16
16
16
16
16
16
16
U
U
U
U
0xFFFF
0xFFFF
0x01FF
0x0000
Line cycle accumulation mode count.
Zero-crossing timeout count.
Computation mode register.
PGA gains at ADC inputs (see Table 22).
0xE610 to
0xE616
Reserved
This register should be ignored.
0xE617
0xE618
0xE700
0xE701
0xE702
0xE703
0xE704
CHSIGN
CONFIG
MMODE
ACCMODE
LCYCMODE
PEAKCYC
SAGCYC
R
R/W
R/W
R/W
R/W
R/W
R/W
16
16
8
8
8
8
8
16
16
8
8
8
8
8
U
U
U
U
U
U
U
N/A
0x0000
0x1C
0x00
0x78
0x00
0x00
Power sign register.
Configuration register.
Measurement mode register.
Accumulation mode register.
Line accumulation mode.
Peak detection half line cycles.
Sag detection half line cycles.
0xE705
Reserved
This register should be ignored.
0xE706
0xE707
0xE7E3
HSDC_CFG
Version
Reserved
R/W
R/W
R/W
8
8
8
8
8
8
U
U
U
0x00
0x00
HSDC configuration register.
Version of die.
Register protection (see the Register
Protection section).
0xE7FE
Reserved
Register protection key (see the Register
Protection section).
0xEBFF
Reserved
8
8
This address can be used in manipulating
the SS/HSA pin when SPI is chosen as
the active port (see the Communication
section for details).
0xEC00
Reserved
This register should be ignored.
0xEC01
CONFIG2
R/W
8
8
U
0x00
Configuration register (see Table 29).
1
2
3
4
R is read, and W is write.
32 ZP is a 24- or 20-bit, signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE is a 24-bit, signed register
that is transmitted as a 32-bit word that is sign extended to 32 bits.
U indicates an unsigned register, and S indicates a signed register in twos complement format.
N/A is not applicable.
REGISTER DESCRIPTIONS
Table 16. HPFDIS Register (Address 0x4389)
Bits
[23:0]
Default Value
0x000000
Description
When HPFDIS = 0x000000, all high-pass filters in voltage and current channels are enabled.
When the register is set to any nonzero value, all high-pass filters are disabled.
Table 17. IPEAK Register (Address 0xE500)
Bits
[31:27]
26
25
24
[23:0]
Bit Name
Reserved
IPCHANNEL2
IPCHANNEL1
IPCHANNEL0
IPEAKVAL[23:0]
Default Value
0x00000
0x0
0x0
0x0
0x0
Description
These bits should be ignored.
The C or F current channel generated the IPEAKVAL[23:0] value.
The B or E current channel generated the IPEAKVAL[23:0] value.
The A or D current channel generated the IPEAKVAL[23:0] value.
Current channel peak value
Table 18. VPEAK Register (Address 0xE501)
Bits
[31:24]
[23:0]
Bit Name
Reserved
VPEAKVAL[23:0]
Default Value
0x00000
0x0
Description
These bits should be ignored.
Voltage channel peak value.
Rev. A | Page 40 of 48
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